
/**
  @file drv_acc.h

  @date 2010-02-26

  @version v5.1

  The file implement driver acc IOCTL defines and macros
*/

#ifndef _DRV_APP_H_
#define _DRV_APP_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "drv_api.h"

#define  _DRV_CPU_ACC_M_
#define  _DRV_FIB_ACC_M_
#define  _DRV_IPFIX_ACC_M_

#define DRV_GET_ACC_TYPE()

#define DRV_HSS_LOCK(lchip_offset)          sal_mutex_lock(p_drv_master[lchip_offset]->p_hss_mutex)
#define DRV_HSS_UNLOCK(lchip_offset)        sal_mutex_unlock(p_drv_master[lchip_offset]->p_hss_mutex)

#define DRV_I2C_RCBUS_WRDATA_REG_OFFSET  0x12
#define DRV_I2C_RCBUS_ADDR_REG_OFFSET  0x11
#define DRV_I2C_RCBUS_CMD_REG_OFFSET  0x13

#define DRV_HSS15G_MACRO_NUM   3
#define DRV_HSS28G_MACRO_NUM   4

#ifdef EMULATION_ENV
 /*EMU_MODIFY, 0x10: pp2*/
extern uint8 g_drv_emu_first_pp_bmp;
#define DRV_OPER_BMP_MASK_PP(lchip, oper_bmp, tbl_id) { \
        if((TABLE_ENTRY_TYPE(lchip, tbl_id) == MEM_TYPE_PER_PP || TABLE_ENTRY_TYPE(lchip, tbl_id) == MEM_TYPE_PER_DP || TABLE_ENTRY_TYPE(lchip, tbl_id) == MEM_TYPE_PEER_PP || TABLE_ENTRY_TYPE(lchip, tbl_id) == MEM_TYPE_PEER_DP) && (((oper_bmp >> 2) & 0x0F) == 0))\
        {\
            oper_bmp |= g_drv_emu_first_pp_bmp;\
        }\
    }
#else
#define DRV_OPER_BMP_MASK_PP(lchip, oper_bmp, tbl_id) 
#endif

#if(SDK_WORK_PLATFORM == 1)
#define DRV_APP_REG_IOW(lchip,tbl_id,data,oper_bmp)  \
       do\
       {\
          uint64 cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG) | (uint64)oper_bmp<<DRV_BITS_PER_WORD;\
          ret = DRV_IOCTL(lchip, 0,cmd, data);\
       }while(0)

#define DRV_APP_REG_IOR(lchip,tbl_id,data,oper_bmp)  \
       do\
       {\
          uint64 cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG) | (uint64)oper_bmp<<DRV_BITS_PER_WORD;\
          ret = DRV_IOCTL(lchip, 0,cmd, data);\
       }while(0)

#define DRV_APP_TBL_IOW(lchip,tbl_id,index,data,oper_bmp)  \
       do\
       {\
          uint64 cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG) | (uint64)oper_bmp<<DRV_BITS_PER_WORD;\
          ret = DRV_IOCTL(lchip, index,cmd, data);\
       }while(0)

#define DRV_APP_TBL_IOR(lchip,tbl_id,index,data,oper_bmp)  \
       do\
       {\
          uint64 cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG) | (uint64)oper_bmp<<DRV_BITS_PER_WORD;\
          ret = DRV_IOCTL(lchip, index,cmd, data);\
       }while(0)

 #define DRV_ACC_WAIT_SLEEP  sal_task_sleep(1);

#else
#define DRV_APP_REG_IOW(lchip,tbl_id,data,oper_bmp)  \
    do\
    {\
        uint8  _oper_bmp = 0;\
        if (p_drv_master[lchip]->dev_type >= DRV_ARCTIC){\
        uint8  drv_bmp = 0;\
        drv_bmp = p_drv_master[lchip]->core_bmp[g_drv_chip[lchip].core_id][1] | p_drv_master[lchip]->pp_bmp[g_drv_chip[lchip].pp_id] | 3;\
        _oper_bmp = (oper_bmp? (oper_bmp&drv_bmp): 0xFF) & p_drv_master[lchip]->oper_mask[TABLE_ENTRY_TYPE(lchip, tbl_id)];\
        DRV_OPER_BMP_MASK_PP(lchip, _oper_bmp, tbl_id);}\
        ret =drv_usw_chip_reg_write(lchip,tbl_id,0,_oper_bmp,(uint32*)data);\
    }while(0)

#define DRV_APP_REG_IOR(lchip,tbl_id,data,oper_bmp)  \
    do\
    {\
        uint8  _oper_bmp = 0;\
        if (p_drv_master[lchip]->dev_type >= DRV_ARCTIC){\
        uint8  drv_bmp = 0;\
        drv_bmp = p_drv_master[lchip]->core_bmp[g_drv_chip[lchip].core_id][1] | p_drv_master[lchip]->pp_bmp[g_drv_chip[lchip].pp_id] | 3;\
        _oper_bmp = (oper_bmp? (oper_bmp&drv_bmp): (p_drv_master[lchip]->core_bmp[g_drv_chip[lchip].core_id][1] |\
                    p_drv_master[lchip]->pp_bmp[g_drv_chip[lchip].pp_id] | 1)) &\
                    p_drv_master[lchip]->oper_mask[TABLE_ENTRY_TYPE(lchip, tbl_id)];\
        DRV_OPER_BMP_MASK_PP(lchip, _oper_bmp, tbl_id);}\
        ret =drv_usw_chip_reg_read(lchip,tbl_id,0,_oper_bmp,(uint32*)data);\
    }while(0)

#define DRV_APP_TBL_IOW(lchip,tbl_id,index,data,oper_bmp) \
    do\
    {\
        uint8  _oper_bmp = 0;\
        if (p_drv_master[lchip]->dev_type >= DRV_ARCTIC){\
        uint8  drv_bmp = 0;\
        drv_bmp = p_drv_master[lchip]->core_bmp[g_drv_chip[lchip].core_id][1] | p_drv_master[lchip]->pp_bmp[g_drv_chip[lchip].pp_id] | 3;\
        _oper_bmp = (oper_bmp? (oper_bmp&drv_bmp): 0xFF) & p_drv_master[lchip]->oper_mask[TABLE_ENTRY_TYPE(lchip, tbl_id)];\
        DRV_OPER_BMP_MASK_PP(lchip, _oper_bmp, tbl_id);}\
        ret = p_drv_master[lchip]->ioctl_cb[TABLE_IOCTL_TYPE(lchip, tbl_id)][DRV_IOC_WRITE](lchip, index, DRV_IOW(tbl_id, DRV_ENTRY_FLAG), _oper_bmp, (uint32*)data);\
    }while(0)

#define DRV_APP_TBL_IOR(lchip,tbl_id,index,data,oper_bmp) \
    do\
    {\
        uint8  _oper_bmp = 0;\
        if (p_drv_master[lchip]->dev_type >= DRV_ARCTIC){\
        uint8  drv_bmp = 0;\
        drv_bmp = p_drv_master[lchip]->core_bmp[g_drv_chip[lchip].core_id][1] | p_drv_master[lchip]->pp_bmp[g_drv_chip[lchip].pp_id] | 3;\
        _oper_bmp = (oper_bmp? (oper_bmp&drv_bmp): (p_drv_master[lchip]->core_bmp[g_drv_chip[lchip].core_id][1] |\
                    p_drv_master[lchip]->pp_bmp[g_drv_chip[lchip].pp_id] | 1)) &\
                    p_drv_master[lchip]->oper_mask[TABLE_ENTRY_TYPE(lchip, tbl_id)];\
        DRV_OPER_BMP_MASK_PP(lchip, _oper_bmp, tbl_id);}\
        ret = p_drv_master[lchip]->ioctl_cb[TABLE_IOCTL_TYPE(lchip, tbl_id)][DRV_IOC_READ](lchip, index, DRV_IOR(tbl_id, DRV_ENTRY_FLAG), _oper_bmp, (uint32*)data);\
    }while(0)

#define DRV_ACC_WAIT_SLEEP
#endif

extern int32
drv_usw_get_cam_info(uint8 lchip, uint8 hash_module, uint32* tbl_id, uint8* num);

extern int32
drv_usw_get_cam_info(uint8 lchip, uint8 hash_module, uint32* tbl_id, uint8* num);

extern int32
drv_usw_get_cam_info(uint8 lchip, uint8 hash_module, uint32* tbl_id, uint8* num);

extern int32
drv_usw_acc_fdb_cb(uint8 lchip, uint8 hash_module, drv_acc_in_t* in, drv_acc_out_t* out);

extern int32
drv_usw_acc_host0(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

extern int32
drv_usw_acc_hash(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

extern int32
drv_usw_acc_mac_limit(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

extern int32
drv_usw_acc_ipfix(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

extern int32
drv_usw_acc_cid(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

extern int32
drv_usw_acc_mpls(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

extern int32
drv_usw_acc_gemport(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

extern int32
drv_usw_acc_aging(uint8 lchip, uint8 hash_module, drv_acc_in_t* acc_in, drv_acc_out_t* acc_out);

extern int32
drv_usw_acc_init(uint8 lchip);
#ifdef __cplusplus
}
#endif
#endif /*end of _DRV_ACC_H*/
